FB-CPU RTL Design
Within the scope of this project, RTL design of a processor named FB-CPU with Verilog language and various code snippets written in machine language on the designed processor will be written. At the end of the project, it will be observed how RAM, Control Unit and Stores in a simple processor can work together and execute code snippets in machine language. FBCPU demo will be made on Basys3 FPGA development board to be used.
Detailed project description: Will be announced after midterm